Front-end Design Concepts
The first section is a quick revision of logic circuits, a course that is usually taught in the first or second year of Engineering at the under-graduate level. The second section explains the motivation behind modelling hardware, introduces concepts of clocks and resets, RTL and testbench. The third section is a deep dive into verification and covers various aspects therein.
This module offers a comprehensive overview of Front-end Design. It aims to increases awareness of the topic at large and prepares you to appreciate subsequent modules in this series.
Unit Description :
- Digital circuits revisited A quick recap of digital logic basics. These concepts will prove useful in understanding subsequent chapters in this module.
- Front-end digital design [Part 1] An introduction to concepts in Front-end Digital Design.
- Front-end digital design [Part 2] Delves into, what is arguably the most important process in Digital IC design, viz. Verification.
Pre-requisites: Coursework in or familiarity with digital logic circuits
A Practical guide to Verilog
This is a practical guide to the Verilog Hardware Description Language (HDL). A significant portion of the language follows conventions similar to traditional programming languages like C. However, given its focus towards modeling hardware, certain constructs and concepts are unique to Verilog.
This module offers a comprehensive overview of the Verilog language, centered around its role in modeling hardware. Upon completing this module successfully, you should be able to implement simple designs in Verilog and verify their functionality.
- Practical guide to Verilog [Part 1] Introduces an exhaustive list of Verilog language syntax and semantics.
- Practical guide to Verilog [Part 2] Detailed analysis of Expressions and Assignments in Verilog.
- Practical guide to Verilog [Part 3] Free! Detailed overview of blocks, with special emphasis on how blocks are built from leaf level constructs introduced earlier.
- Practical guide to Verilog [Part 4] Detailed analysis of statements, functions and tasks in Verilog.
Pre-requisites: Familiarity with digital front-end design concepts, such as hardware modeling, clocks, resets, simulation etc.
RTL & Testbench Coding: A Case Study
This is a practical guide to RTL implementation and Verification. This module offers a typical case study of the process and method of writing RTL and verifying its functionality, just the way it is done in the industry. Upon completing this module successfully, you should be able to implement designs in Verilog efficiently and within the ambit of industry-standard processes and guidelines.
RTL & Testbench Coding [Part 1] A case study of a detailed design plan covering RTL functionality, Verification strategy, Testbench architecture and Testcases.
RTL & Testbench Coding [Part 2] Hands-on guide to RTL, Testbench and Testcase implementation.
RTL & Testbench Coding [Part 3] Hands-on guide to RTL, Testbench and Testcase implementation.
Pre-requisites: Working knowledge of Verilog HDL.